1. Field of the Invention
The invention relates generally to semiconductor devices and manufacturing methods thereof and, more particularly, relates to structures in which it is intended to enhance characteristics of semiconductor devices using a thin conductor film as an electrode or an electric interconnection, and manufacturing methods thereof.
2. Description of the Background Art
With increased integration density of a semiconductor device in recent years, techniques of a higher level have been needed and developed for forming a conductor film constituting an electrode or an electric interconnection. Particularly, as a semiconductor is miniaturized and more layers are formed therein for higher integration density, a thinner conductor film is required for realizing planarization.
A description will be made in the following as to a conventional manufacturing process of a semiconductor device using a thin conductor film as an electrode or an electric interconnection, referring to FIGS. 1A to 1C.
Firstly, an insulating film 2 including an oxide silicon film or the like for interlayer insulation is formed on a p-type silicon substrate 1 having an impurity concentration of the order of 1.times.10.sup.15 /cm.sup.3 by the well-known thermal oxidation method. Furthermore, a conductor thin film 3 for electrode interconnection made of polysilicon is deposited by the chemical vapor deposition and then treated as a desired electrode pattern using a photolithography and an etching technique. Subsequently, an insulating film 4 for interlayer insulation and smooth coating is deposited by the chemical vapor deposition (see FIG. 1A). Then, a contact hole 6 for electrically connecting the conductor thin film 3 to an external circuit is apertured by the photolithography and dry etching technique using a resist mask 7 and by the wet etching technique (see FIG. 1B). After that, an aluminum layer for electrically connecting the electrode with the external circuit is deposited by the sputtering technique and treated into a desired configuration by the photolithography and the etching technique to form an interconnection layer 5 made of aluminum (see FIG. 1C).
In accordance with the conventional semiconductor device structured as stated above, when the conductor thin film 3 is made thin for planarization with the miniaturization, part of the conductor thin film 3 tends to be etched by over etching for selectively removing the insulating film 4 at the time of forming the contact hole 6 as shown in FIG. 1B. Therefore, the contact hole 6 is formed in this portion, leading to the silicon substrate 1 through the underlying insulating film 2. In this case, there has been a problem that the silicon substrate 1 and the conductor thin film 3 are electrically connected to each other due to the formation of the interconnection layer 5.
There have been conventional techniques for solving the above-mentioned problem, in which a polysilicon layer 8 is selectively formed between the conductor thin film 3 and the silicon substrate 1 in a region in the vicinity of the contact hole 6, as shown in FIG. 2, to prevent etching from proceeding to the surface of the silicon substrate 1 (for example, see Japanese Patent Laying-Open No. 63-268258).
In the structure disclosed in the above-mentioned publication, however, there were problems as follows.
Now suppose that the structure shown in FIG. 2 is employed for forming an electrode, an electric interconnection or a resistor as shown in FIGS. 3 and 4. The structure shown in FIG. 3 and FIG. 4 (a sectional view taken along the line A--A of FIG. 3) is obtained by forming an insulating film 12 on a silicon substrate 11, selectively depositing a conductor layer 18 made of polysilicon on the surface of it, furthermore, depositing a conductor thin film 13 of polysilicon over the entire surface of the silicon substrate 11, and then applying a photolithography and etching to a resist film 19 to pattern the same. After that, in selectively removing the conductor thin film 13 by etching, the state shown in FIG. 5A is shifted to the state shown in FIG. 5B with the conductor thin film 13 and the conductor layer 18 being selectively removed in the cross section B--B of FIG. 3. In the cross section C--C of FIG. 3, however, only the conductor thin film 13 must be selectively removed by etching since there is no conductor layer 18. Therefore, while etching of the conductor layer 18 proceeds in the cross section B--B, the etching proceeds from the state of FIG. 6A even after the conductor thin film 13 has been removed, and as shown in FIG. 6B, etching of the side portion of the conductor thin film 13, that is to say side etching, and etching of the surface of the insulating film 12 proceed in the cross section C--C. Accordingly, there is a problem that the pattern configuration of the conductor thin film 13 in the cross section C--C becomes narrow.
It is considered that the resist film 19 is patterned so as to cover the whole region in which the conductor layer 18 is selectively formed to effect etching of the conductor thin film 13 as shown in FIGS. 7 and 8. In accordance with the method, a portion 13a indicated by a two-dot chain line may be only removed by etching in the cross section B--B of FIG. 7 as shown in FIG. 9A. Accordingly, the portion 13a indicated by the two-dot chain line is removed and patterns of an electric interconnection and a resistor and so on including the conductor thin film 13 are formed in the cross section C--C of FIG. 7 in the same period of time as shown in FIG. 9B.
In this case, however, it is essential for the resist film 19 to cover the entire surface of the region of the conductor layer 18 without fail and if even a slight slipping of patterning is caused, part of the conductor layer 18 remains after etching of the conductor thin film 13. Therefore, there is a problem that it is necessary to take a margin by which the resist film 19 may cover the entire surface on the region of the conductor layer 18 even if a little slipping off of patterning is caused and that the area occupied by the electric interconnection and the resistor to be formed becomes unnecessarily large.
Additionally, in the technique of the above-mentioned publication, since the conductor thin film 3 and the polysilicon layer 8 are directly in contact with each other, an interlayer insulating film must be interposed between the conductor film deposited for forming the conductor thin film 3 and the polysilicon layer deposited for forming the polysilicon layer 8 in order to utilize each of them as an individual device element in other regions. In other words, there is a problem that it is difficult to form the conductor thin film 3 and the polysilicon layer 8 simultaneously in forming a conductor layer which exists as an individual device element in other region.